RISC-V si 32bit RISC
ARM (Cortex M) is 32bit RISC
RISC means: Reduced Instruction Set Computing
- For more info concerning Cortex-Mx see here.
- For more info concerning RISC-V see here for English and here for Italian.
Brief introduction to RISC-V
RISC-V is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use.
A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
RISC-V si 32bit RISC is born in USA universities.
There is 32bit and 64bit version and 128bit is possible according to the architecture.
RISC-V are available for commercial and non commercial organization (IP is free).
There are several versions identified as shown below.
M – Integer multiplication and division
A – Atomic instructions
F – Single-Precision Floating-Point
D – Double-Precision Floating-Point
Q – Quad-Precision Floating-Point
C – Standard extension for compressed instructions
G – encompasses the options MAFD
There are also some proposed extension are:
B – Bit manipulation
P – Packed-SIMD
V – Vector operation
In terms of performance it is difficult to say which of RISC-V(SiFive) and ARM is the best performer because both companies regularly release new cores to outperform each other.
To date (Nov 2021) ARM seems to have the best performing cores.
The main advance for SW development is that for RISC-V cpu there are a lot the IDE that are free and are based on Eclipse, GCC and GDB.